BÀI 9 : TIMER 0 PIC18F4431 XC8

9:18:00 PM
GIỚI THIỆU VỀ TIMER 0 CỦA PIC18F4431
1. Đặc điểm của Timer 0 PIC18F4431
- Là Timer/Counter 8bit hoặc 16bit.
- Có thể đọc và ghi.
- Có bộ chia trước 8 bit có thể lập trình bằng phần mềm.
- Có thể lựa chọn nguồn xung clock bên trong hoặc bên ngoài.
- Xảy ra hiện tượng ngắt khi tràn từ FFh - 00h khi chọn Timer/Counter 8bit và tràn từ FFFFh – 0000h khi chọn Timer/Counter là 16bit.
- Cho phép lựa chọn tác động cạnh cho xung clock bên ngoài.
2. Các thanh ghi điều khiển Timer 0 PIC18F4431.
a. T0CON TIMER0 CONTROL REGISTER
thanh ghi t0con
- Bit 7 : TMR0ON bit điều khiển Timer 0.
1 = Cho phép Timer chạy.
0 = Timer dừng.
- Bit 6 : T016BIT điều khiển Timer 16bit.
1 = Là Timer/Counter 8bit.
0 = Là Timer/Counter 16bit.
- Bit 5 : T0CS Bit lựa chọn nguồn xung clock cho Timer 0.
1 = Xung đưa đến chân T0CKI.
0 = Xung clock bên trong.
- Bit 4 : T0SE bit lựa chọn cạnh tích cực.
1 = Tính cực cạnh xuống trên chân T0CKI.
0 = Tích cực cạnh lên trên chân T0CKI.
- Bit 3 : PSA bit lực chọn bộ prescaler.
1 = Không sự dụng bộ prescaler.
0 = Sự dụng bộ prescaler.
- Bit 2,1,0  <T0PS(2:0)> bit lựa chọn tỷ lệ prescaler.
3. Sơ đồ khối của Timer/Counter.
a. Timer/Counter 8 bit.

b. Timer/Counter 16 bit.
- Đây là ảnh mô phỏng protues.

timer 0 pic18f4431

- Đây là code chương trình.
#include <xc.h>
#include <stdio.h>
#include <stdlib.h>
// CONFIG1H
#pragma config OSC = XT         // Oscillator Selection bits (XT oscillator)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal External Oscillator Switchover bit (Internal External Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled)
// BORV = No Setting

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDPS = 32768     // Watchdog Timer Postscale Select bits (1:32768)
#pragma config WINEN = OFF      // Watchdog Timer Window Enable bit (WDT window disabled)

// CONFIG3L
#pragma config PWMPIN = OFF     // PWM output pins Reset state control (PWM outputs disabled upon Reset (default))
#pragma config LPOL = HIGH      // Low-Side Transistors Polarity (PWM0, 2, 4 and 6 are active-high)
#pragma config HPOL = HIGH      // High-Side Transistors Polarity (PWM1, 3, 5 and 7 are active-high)
#pragma config T1OSCMX = OFF    // Timer1 Oscillator MUX (Standard (legacy) Timer1 oscillator operation)

// CONFIG3H
#pragma config FLTAMX = RC1     // FLTA MUX bit (FLTA input is multiplexed with RC1)
#pragma config SSPMX = RC7      // SSP I/O MUX bit (SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7.)
#pragma config PWM4MX = RB5     // PWM4 MUX bit (PWM4 output is multiplexed with RB5)
#pragma config EXCLKMX = RC3    // TMR0/T5CKI External clock MUX bit (TMR0/T5CKI external clock input is multiplexed with RC3)
#pragma config MCLRE = OFF      // MCLR Pin Enable bit (Disabled)

// CONFIG4L
#pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = OFF        // Low-Voltage ICSP Enable bit (Low-voltage ICSP disabled)

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000200-000FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (001000-001FFF) not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (002000-002FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (003000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot Block (000000-0001FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000200-000FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (001000-001FFF) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (002000-002FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (003000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0001FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000200-000FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (001000-001FFF) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (002000-002FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (003000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0001FFh) not protected from table reads executed in other blocks)

unsigned int Count = 0;
void main(void)
{
    TRISCbits.TRISC0 = 0;
    TMR0 = 0x05;
    T0CONbits.TMR0ON = 1;
    T0CONbits.T016BIT = 1;
    T0CONbits.T0CS = 0;
    T0CONbits.PSA=0;    
    T0CONbits.T0PS0=1;
    T0CONbits.T0PS1=0;
    T0CONbits.T0PS2=0;
    while(1)
    {
        if(INTCONbits.TMR0IF == 1){
        INTCONbits.TMR0IF = 0;
        TMR0 = 0x05;
        Count++;
            if(Count==5)
            {
                Count =0;
                PORTCbits.RC0 ^= 1;   //toggle the LED
            }
    }
    }
}
- Link download project Click here

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